Lower Body part, electronics are inside the hexapod. MAX3232CPE with some caps for
RS232<->LVTTL level shifting on the left, ROK 101 007 bluetooth module in the middle.
Those modules are connected to two UARTs on the FPGA via a 6 wire
cable (GND, 3.3V, RXD, TXD, RTS, CTS - CTS/RTC currently unused).
This is the board that's mounted just below the upper body part, where the FPGA board is
plugged into from the other side. Power on the top right. 2x UART on the pin header in the
lower left corner. 18x3 pin headers for servos. The pin header in the lower right corner
originally were the UARTs, but without power supply, just GND, TXD, RXD.
Whole assembly again, servos not plugged in yet. FPGA board on top, plugged via two 2x20 pin headers
into board mounted on the upper body.
Servos plugged in, serial cable in the foreground, serial board with maxim chip behind
and the small "Pömpel" is the bluetooth antenna.
A couple more images and highres versions: http://wuselfuzz.de/hexapod/images/botpix090713/FPGA CODE
I had some issues with the new FPGA board, but it's looking brighter now.
At first, I ported the CPU + Bootloader ROM + UART over to the new board. Since the new board
has a 66 MHz OSC (which is halved in the FPGA design), I decided to let the CPU run at 33 MHz.
So the bootloader was working, but the RAM on the board is different to the Digilent board - the
S3 Starter Kit board had 1 MB of 10ns 32 bit RAM, the new board only has 70ns 8 bit RAM.
And that megabyte of RAM was where my code was running from.
For now, I used more of the FPGA internal RAM blocks to get a whopping 16kBytes of memory
- 8k bootloader "ROM" which is just preinitialized RAM and another 8k block at the same memory
location where I previously had 1 MB.
A few tests then have shown that servo control and the bootloader actually work.
The maximum amount of RAM I could get from the FPGA RAM blocks is 24kBytes. (12 blocks
with 2k each, I need 4 blocks to form 8k 32 bit RAM).
And the external RAM on the FPGA board is slow.
The demo code running in the youtube video is ~50kbytes large.
My current idea is to implement another CPU on the FPGA, a simple 8 bit CPU maybe running at 10 MHz.
This could communicate with the faster 32 bit CPU via a block of dual ported RAM or an SPI interface.
Then stripping down the 32 bit code to the bare minimum neccessary to do inverse kinematic calculations
and performing some linear interpolated EE movements. If that fits into maybe 16k, I can just use
the Plasma CPU as a realtime co processor and do higher level stuff on my slow 8 bit CPU. SOFTWARE
Nothing new on movement algorithms here, as previously mentioned, I have to optimize stuff for size so
I can let it run.
What I'm currently trying to figure out is the HCI protocol to talk to the bluetooth module. The test code for this fits on FPGA internal RAM.